This invention relates to integrated circuits (ICs) and data processing systems, in particular to a method of designing integrated circuits.
Continuing advances in semiconductor technology have made possible the integration of increasingly complex functionality on a single chip. Single large chips are now capable of performing the functions of entire multi-chip systems of a few years ago. While providing new opportunities, multi-million-gate systems-on-chip pose new challenges to the system designer. In particular, conventional design and verification methodologies are often unacceptably time-consuming for large systems-on-chip.
Hardware design reuse has been proposed as an approach to addressing the challenges of designing large systems. In this approach, functional blocks (also referred to as cores or intellectual property, IP) are pre-designed and tested for reuse in multiple systems. The system designer then integrates multiple such functional blocks to generate a desired system. The cores are often connected to a common communication bus, and are controlled by a central microcontroller or CPU.
The hardware design reuse approach reduces the redundant re-designing of commonly-used cores for multiple applications. At the same time, the task of interconnecting the cores is often relatively time-consuming and error-prone. In common industry practice, large amounts of hardware description language (HDL) code are written manually for interconnecting the various cores of the system. If one designer changes the interface signals of a block but does not communicate the change to another designer responsible for the interconnection code, valuable time is wasted debugging the design.
In order to verify that a given HDL design performs correctly, it is common to build a behavioral (functional) model of the algorithm in a software language such as C or C++. The results of the software model are then compared against those of the HDL model. The software and HDL model must be kept consistent with each other. Changes to one model must be reflected in the other. Making such changes is typically time-consuming, and increases the chance of introducing inconsistencies between the two models. The complexity of making such changes increases if large teams of engineers are involved in the design process.
Core integration and design maintenance are particularly difficult for cores having complex and/or core-specific interfaces. Core integration and design maintenance are two of the major challenges of designing large systems integrated on a single chip using the hardware design reuse approach.